1. Field of the Invention
The present invention relates to a memory device.
2. Description of the Related Art
A D-RAM (dynamic random access memory) of the prior art will be described below with reference to FIG. 1 and FIG. 2 specifically showing some of circuits shown in FIG. 1. The D-RAM has plural, (n+1) pairs of bit lines BL0 and BLB0, BL1 and BLB1, . . . , and BLn and BLBn; plural, (m+1) word lines WL0, WL1, . . . , and WLm which intersect the bit lines BL0 and BLB0, BL1 and BLB1, . . . , and BLn and BLBn; a matrix of a plurality of D-RAM memory cells 10-0 {MC0-1, MC1-0, MC2-0, . . . , MC(m−1)−0, and MCm−0}, 10-1 {MC0-1, MC1-1, MC02-1, . . . , MC(m−1)−1, and MCm−1}, and 10-n{MC0-n, MC1-n, MC2-n, . . . , MC(m−1)−n, and MCm−n}, each of which is connected to an intersection of each bit line and each word line; and sense amplifiers 30-0, 30-1, . . . , and 30-n connected to the memory cells 10-0, 10-1, . . . , and 10-n, each of which comprises a plurality of memory cells, through the bit lines BL0 and BLB0, BL1 and BLB1, . . . , and BLn and BLBn, respectively.
Each of the memory cells 10-0 {MC0-0, MC1-0, MC2-0, . . . , MC(m−1)−0, and MCm−0}, 10-1 {MC0-1, MC1-1, MC2-1, . . . ,MC(m−1)−1, and MCm−1}, . . . , and 10-n {MC0-n, MC1-n, MC2-n, . . . , MC(m−1)−n, and MCm−n} comprises, for example, an N-channel (or P-channel) type MOS-FET Q which functions as a switching transistor, and a capacitor C connected in series with the MOS-FET Q.
The drains of the MOS-FETs Q of the memory cells MC0-0, MC2-0, MC4-0 , . . . of the memory cell 10-0, the memory cells MC0-1 , MC2-1, MC4-1 , . . . of the memory cell 10-1, . . . , and the memory cells MC0-n, MC2-n, MC4-n, . . . of the memory cell 10-n are connected to the bit lines BL0, BL1, BL2, . . . , and BLn, the gates thereof are connected to the word lines WL0, WL2, WL4, . . . , and the sources thereof are connected to cell plate potential lines VL to which a common cell plate potential Vcp is applied, through the capacitors C.
The drains of the MOS-FETs Q of the memory cells MC1-0 , MC3-0 , MC5-0 , . . . of the memory cell 10-0, the memory cells MC1-1 , MC3-1, MC5-1, . . . of the memory cell 10-1, . . . , and the memory cells MC1-n, MC3-n, MC5-n, . . . of the memory cell 10-n are connected to the bit lines BLB0, BLB1, BLB2, . . . . , and BLBn, the gates thereof are connected to the word lines WL1, WL3, WL5, . . . , and the sources thereof are connected to the cell plate potential lines VL to which the common cell plate potential Vcp is applied, through the capacitors C.
Each of the sense amplifiers 30-0, 30-1, . . . , and 30-n comprises P-channel type MOS-FETs Q1 and Q2 which are connected in series between the bit lines BL0 and BLB0, between the bit lines BL1 and BLB1, . . . , and between the bit lines BLn and BLBn and whose gates are connected to the bit lines BLB0, BLB1, . . . , BLBn and the bit lines BL0, BL1, . . . , and BLn, respectively; and N-channel type MOS-FETs Q3 and Q4 which are connected in series between the bit lines BL0 and BLB0, between the bit lines BL1 and BLB1, . . . , and between the bit lines BLn and BLBn and whose gates are connected to the bit lines BLB0, BLB1, . . . , BLBn and the bit lines BL0, BL1, . . . , and BLn, respectively. Each sense amplifier is configured so that a driving signal from a sense amplifier driver is supplied to the midpoint of connection between the P-channel type MOS-FETs Q1 and Q2 and the midpoint of connection between the N-channel type MOS-FETs Q3 and Q4.
Data read out from the memory cells 10-0, 10-1, . . . , and 10-m, each of which comprises a plurality of memory cells, are transmitted to a read DB (data bus) through the sense amplifiers 30-0, 30-1, . . . , and 30-n and read gates 40-0, 40-1, . . . , and 40-n. Data from a write DB (data bus) are transmitted to and written in the memory cells 10-0, 10-1, . . . , and 10-m through write gates 50-0, 50-1, . . . , and 50-n and the sense amplifiers 30-0, 30-1, . . . , and 30-n. 
A D-RAM of the prior art shown in FIG. 3 comprises the D-RAM shown in FIG. 1, and additional read gates 41-0, 41-1, . . . , and 41-n which are provided for the sense amplifiers 30-0, 30-1, . . . , and 30-n, respectively. When a transfer gate 20 is on, data read out from the memory cells 10-0, 10-1, . . . , and 10-m, each of which comprises a plurality of memory cells, are transmitted to the read DB (data bus) through the sense amplifiers 30-0, 30-1, . . . , and 30-n, the transfer gate 20, D latches 60-0, 60-1, . . . , and 60-n and the read gates 41-0, 41-1, . . . , and 41-n. When the transfer gate 20 is off, the memory device shown in FIG. 3 operates in the same manner as the memory device shown in FIG. 1. The other configuration of the memory device is the same as that of the memory device shown in FIG. 1.
The D-RAM of the prior art shown in FIG. 3 has the following problem. Since data read out from the memory cells 10-0, 10-1, . . . , and 10-m pass through the sense amplifiers 30-0, 30-1, . . . , and 30-n when the data are transmitted to the D latches 60-0, 60-1, . . . , and 60-n, this makes it impossible to make access to the sense amplifiers 30-0, 30-1, . . . , and 30-n during the passage of the data, or the read data overwrite data of the sense amplifiers 30-0, 30-1, . . . , and 30-n. 
The above-mentioned D-RAM has a problem of a long access time to a row line. This result from the fact that data of the memory cells of the D-RAM must be amplified and latched by the sense amplifiers before the data are read out. This is a fundamental problem of the D-RAM.
In order to solve the above-mentioned problems, a plurality of D-RAMs or a D-RAM having a bank structure is used so that the D-RAM operates using banks. More specifically, when access to a bank is being made, another bank is activated to previously enter a ready state so that data are read out consecutively. This is called interleaving. This allows apparently hiding the setup time (tRCD) and the reset time (tPR) required for the D-RAM.
It is possible that a plurality of D-RAMs or the D-RAM having the bank structure is used in order that the D-RAM having a conventional configuration may realize the operation using banks. When a plurality of D-RAMs is used, each D-RAM is not good in area efficiency, but each D-RAM is not limited in operation. On the other hand, the D-RAM having the bank structure is good in area efficiency because a part of a circuit is common among banks, whereas each bank is partly limited in operation.
The D-RAM has properties that its larger storage capacity yields its higher area efficiency, while its smaller storage capacity yields its lower area efficiency, similarly to other types of memories. A D-RAM having a multibank structure causes a reduction in area efficiency. Assume that a mixed D-RAM comprises banks of varying minimum units (i.e., blocks), e.g., a 2-Mbit block, a 1-Mbit block, and a 512-Kbit block. If a 4-Mbit D-RAM is manufactured without consideration of the bank structure, the decreasing order of area efficiency, from highest to lowest, is the 2-Mbit block, the 1-Mbit block, and the 512-Kbit block. When a 4-Mbit D-RAM is manufactured in consideration of the bank structure, the D-RAM can be, however, occupied by up to two banks each having the 2-Mbit block, up to four banks each having the 1-Mbit block, or up to eight banks each having the 512-Kbit block. Even if a D-RAM comprises two banks each having the 1-Mbit or 512-Kbit block, the area efficiency of the D-RAM is not different from that of a D-RAM comprising four banks each having the 1-Mbit block or eight banks each having the 512-Kbit block.
However, a D-RAM having a larger capacity than a necessary capacity, if a small-capacity D-RAM is used, must be used in order that the D-RAM may operate using banks. In terms of area efficiency, the reason is that the size of the block that is the minimum unit of the bank is large. For example, when a user wants to use a 1-Mbit D-RAM in the form of two banks, a D-RAM of at least 2 Mbits must be used to obtain a D-RAM having a two-bank structure, provided that one block equals 1 Mbit.
The above-mentioned D-RAM adopts a bank method in order to apparently hide the access time to a row line requiring consecutive data.
However, the bank method has to be provided with a D-RAM macro (which refers to a group of circuits having functions of a D-RAM), and therefore the method is often disadvantageous in area to an application that needs only a small capacity.
A RAM having a capacity of at least 2 Mbits or more must be packaged to employ a bank structure for, for example, an application that requires a RAM having a capacity of only 1 Mbit, if a macro size that can be provided is 1 Mbit and the use of a plural-bank structure is demanded.
The invention is designed to overcome the foregoing problems. It is an object of the invention to provide a memory device which can minimize a reduction in area efficiency even when the memory device has a small storage capacity and which can hide the access time to a row line.